1. Field of the Invention
The present invention relates generally to mask/wafer control structures which provide for tighter control of both mask production and wafer production by providing the most critical structures for easily accessible measurement, and an algorithm for data placement of the measurement control structures, termed Process Limiting Structures (PLSs), on a photolithographic mask and subsequently on the printed wafers.
2. Discussion of the Prior Art
In the prior art, mask control is typically performed on either Product Control Images (PCIs) or functional features within a chip, wherein a plurality of individual identical chips are typically arranged in a grid on a wafer. Wafer control is based upon either functional features which are difficult to accurately reproduce or designed control features in the kerf(bergies) which do not receive the same data preparation as the chip features. These variations cause measurement inaccuracies which result in exposing the product to quality control risks. In contrast thereto, the PLS structures of the present invention are located at multiple locations throughout each chip, and they receive the same data preparation as the chip, and measurement tools are able to measure the same features at each fabrication step from fabrication of the mask to final formation of the etched features on the wafer. The PLS structure is typically designed to contain the most critical and challenging structures available on the chip.
The existing PCI control scheme provides control based solely upon a single feature type. In contrast thereto, the PLS contains process limiting structures which are representative of product requirements and can contain representative worst-case allowable and critical structures for accessible measurement. Another disadvantage of the PCI strategy is that PCIs are placed manually. In contrast, the PLS placements of the present invention provide significantly improved coverage over the entire reticle and chip by automating the placement to a desired measurement frequency.
Accordingly, it is a primary object of the present invention to provide a mask/wafer control structure and an algorithm for placement of the mask/wafer control structures. The subject invention provides for data placement of measurement control Process Limiting Structures (PLSs) on a mask and the resulting chips on a wafer, and provides for tighter control of both mask manufacture and chip/wafer production.
A further object of the subject invention is the provision of a PLS measurement and control structure which contains multiple features which are representative of product requirements and can contain representative worst-case allowable and critical structures for accessible measurement, as well as easily measurable targets for both mask and wafer level production. The PLS control structure allows for a metrology of the most critical and worst-case allowable features in the level for the mask and the chip/wafer. The present invention advantageously positions PLS control structures at many locations throughout and across the field in both sparse/isolated and dense/nested areas; therefore, across field linewidth variation (ACLV) can be monitored through all stages of production, including mask exposure, mask etch, wafer exposure and pattern transfer.
In accordance with the teachings herein, the present invention provides a PLS placement algorithm and process which describe a compliant grid wherein grid points that occupy areas where PLS structures cannot be placed are moved to the nearest area that they can be placed in or are eliminated. This allows the maintenance of an approximate frequency of placement without having to conform to the rigid constraints of a strictly orthogonal grid.